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[VHDL-FPGA-Verilog] pll

Description: 用VHDL写的数字锁相环程序 pll.vhd为源文件 pllTB.vhd为testbench-pll.vhd : PLL written in VHDL hardware language. pllTB.vhd is a test program for pll.vhd.
Platform: | Size: 111616 | Author: 孙犁 | Hits:

[VHDL-FPGA-Verilog] fdpll

Description: 简单的可配置dpll的VHDL代码。 用于时钟恢复后的相位抖动的滤波有很好的效果， 而且可以参数化配置pll的级数。-simple configurable dpll VHDL code. Clock Recovery for the jitter filtering is a very good result, but can pll configuration parameters of the series.
Platform: | Size: 2048 | Author: 陈德炜 | Hits:

[VHDL-FPGA-Verilog] Div20PLL

Description: 使用VHDL实现锁相环,是个学习VHDL的好例子,与众分享-PLL using VHDL, VHDL is learning a good example, sharing with the public
Platform: | Size: 1024 | Author: | Hits:

[Software Engineering] VHDL_PLL

Description: 介绍了锁相环PLL的实现原理，可以为VHDL实现PLL提供参考。-introduced PLL PLL The principle for VHDL PLL reference.
Platform: | Size: 96256 | Author: CGT | Hits:

[VHDL-FPGA-Verilog] pll

Description: fpga中pll时钟实现的源代码，可实现倍频或分频-pll clock in the FPGA to achieve the source code, can be realized or sub-octave frequency
Platform: | Size: 3072 | Author: 张恒 | Hits:

[VHDL-FPGA-Verilog] PLL

Description: PLL 时钟模块　　Quartus II平台的简单设计实例　附仿真波形-PLL clock module Quartus II platform attached to a simple design example simulation waveforms
Platform: | Size: 806912 | Author: 许东滨 | Hits:

[VHDL-FPGA-Verilog] pll

Description: 用FPGA实现数字锁相环，开发环境为ISE-Using FPGA digital phase-locked loop, development environment for ISE
Platform: | Size: 178176 | Author: 冯勇 | Hits:

[VHDL-FPGA-Verilog] formatter

Description: Actel 基本VHDl模块源代码，包括BCD、LCD、PLL等-Actel basic VHDL source code modules, including BCD, LCD, PLL, etc.
Platform: | Size: 1024 | Author: 曾捷 | Hits:

[VHDL-FPGA-Verilog] pll

Description: 收集的数字锁相环设计相关文章多篇.主要采用VHDL语言进行设计.-Collection of digital phase-locked loop design articles related articles. Mainly VHDL design languages.
Platform: | Size: 10079232 | Author: gk | Hits:

[VHDL-FPGA-Verilog] PLL

Description: verilog PLL的代码，和PLL 的功能介绍，希望能通过，只是简单了点-verilog PLL code, and the function of PLL, the hope, but simply a point
Platform: | Size: 18432 | Author: gjj | Hits:

[Other] pll_funcnl

Description: pll in verilog in the Appendix
Platform: | Size: 227328 | Author: jadedfox | Hits:

[Communication-Mobile] pll

Description: 实现同步时采用锁相环，锁相环实现的原理，及源代码，-Implementation of the principle of phase-locked loop, and the source code,
Platform: | Size: 111616 | Author: qin | Hits:

[VHDL-FPGA-Verilog] pll

Description: 是quartus2的仿真倍频电路，用于产生倍频时钟！-Is a multiplier circuit simulation quartus
Platform: | Size: 332800 | Author: 张宏伟 | Hits:

[Communication-Mobile] pll

Description: 一个实现任意倍频的，输入参考频率未知的pll，已综合实现-frequency multiple rely on dpll，unknown reference input clock
Platform: | Size: 4096 | Author: 刘彻 | Hits:

[Communication-Mobile] EP2C8_pll_example

Description: EP2C8 PLL例化的例子,给不会的人做个参考.专门写的一个.呵呵.不过是Verilog的.-EP2C8 PLL cases of the examples to those who will not be a reference. Specialized write a. Ha ha. But the Verilog.
Platform: | Size: 485376 | Author: tupeng | Hits:

[VHDL-FPGA-Verilog] PLL

Description: 用VHDL和matlab编写的数字锁相环电路。-Matlab with VHDL and digital phase-locked loop circuit prepared.
Platform: | Size: 21504 | Author: 水淼 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 基于FPGA的DDS设计，本程序采用verilog HDL语言编写，使用DDS+Pll倍频-The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
Platform: | Size: 190464 | Author: 赵一 | Hits:

[Other] pll

Description: 摘要:叙述了全数字锁相环的工作原理,提出了应用VHDL 技术设计全数字锁相环的方法,并用复杂可编程逻辑器件CPLD 予以实现,给出了系统主要模块的设计过程和仿真结果。-Abstract: This paper describes the working principle of an all-digital phase-locked loop is proposed application VHDL technical design an all-digital phase-locked loop method, and use complex programmable logic device CPLD to be achieved, given the main modules of the system design process and simulation results .
Platform: | Size: 210944 | Author: lilei | Hits:

[VHDL-FPGA-Verilog] pll

Description: 实现了pll功能，有利于初学者学习pll，采用文本编辑的，利用quartus ii 设计的-Achieved pll function, help beginners learn pll, using a text editor, using quartus ii Design
Platform: | Size: 216064 | Author: ad | Hits:

[VHDL-FPGA-Verilog] AD-PLL

Description: 基于VHDL的全数字锁相环的设计与实现，quartusII的仿真程序。-DPLL based on VHDL Design and Implementation, quartusII the simulation program.
Platform: | Size: 2048 | Author: yzn8625 | Hits:
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